Rahaman, Hafizur., Chattopadhyay, Sanatan.Chattopadhyay, Santanu. (Eds.) (©2012) Progress in VLSI design and test :16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings Berlin ; Springer,MLA Citation
Rahaman, Hafizur., Chattopadhyay, Sanatan.Chattopadhyay, Santanu., eds. Progress In VLSI Design And Test: 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Berlin : Springer, ©2012. Print.
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Progress in VLSI design and test : 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings /
Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay (eds.).
|Names:||Rahaman, Hafizur. | Chattopadhyay, Sanatan. | Chattopadhyay, Santanu.|
|Vernacular:||An Efficient High Frequency and Low Power Analog Multiplier in Current Domain / Anu Gupta and Subhrojyoti Sarkar -- Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator / Biswajit Maity and Pradip Mandal -- Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm / Priyanka Choudhury and Sambhu Nath Pradhan -- Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding / Rahul Shrestha and Roy Paily -- Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects / Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu and Manoj Kumar Majumder -- Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET / Ashutosh Nandi, Ashok K. Saxena and Sudeb Dasgupta -- Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips / R. Jayagowri and K.S. Gurumurthy -- Post-bond Stack Testing for 3D Stacked IC / Surajit Kumar Roy, Dona Roy, Chandan Giri and Hafizur Rahaman -- Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker / Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar and Chittaranjan R. Mandal -- Design of High Speed Vedic Multiplier for Decimal Number System / Prabir Saha, Arindam Banerjee, Anup Dandapat and Partha Bhattacharyya -- An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol / Mamata Dalui and Biplab K. Sikdar -- An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs / Debapriya Basu Roy and Debdeep Mukhopadhyay -- Arithmetic Algorithms for Ternary Number System / Subrata Das, Partha Sarathi Dasgupta and Samar Sensarma -- SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output / Dushyant Juneja, Sougata Kar, Procheta Chatterjee and Siddhartha Sen -- Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting / Goutam Rana, Samir Kumar Lahiri and Chirasree Roy Chaudhuri -- Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin / Chandrabhan Kushwah and Santosh K. Vishvakarma -- Workload Driven Power Domain Partitioning / Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and Chittaranjan R. Mandal -- Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit / Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee and Chandan Kumar Sarkar.
|Published:||Berlin ; Springer, ©2012.|
Lecture notes in computer science ; 7373.
LNCS sublibrary. SL 1, Theoretical computer science and general issues.
|Topics:||Integrated circuits - Very large scale integration - Design and construction - Congresses. | Integrated circuits - Very large scale integration - Testing - Congresses. | Informatique.|
|Genres:||Electronic books. | Conference papers and proceedings. | Computer software.|